作者：Ashish Kumar, Raj Kumar Kokkonda, Subhashish Bhattacharya , Victor Veliadis

單位：Dept. of Electrical and Computer Engineering
North Carolina State University
Raleigh, NC, USA

Abstract——Power modules are connected in series and parallel combinations to meet the voltage and current requirements of various applications, especially in medium voltage high power applications. Avalanche ruggedness of the SiC power MOSFETs need to be established in these connections to assess the reliability of the converters in extreme transient conditions. 1700V SiC MOSFET has potential to replace the conventional 1700V silicon IGBT in medium voltage power converters such as 800V and 1500V railway traction applications. In this paper, single shot avalanche ruggedness of the series-connected and parallel-connected 1700V SiC MOSFETs are characterized using the unclamped inductive test circuit. Single shot avalanche ruggedness of series connected SiC MOSFETs is reported for the first time. In both the connections, the failed MOSFET was observed to be the one which dissipated lower share of the total avalanche energy of the connection.

摘要——電源模塊采用串聯和并聯組合方式連接，以滿足各種應用對電壓和電流的要求，特別是在中壓大功率應用中。需要在這些連接中建立SiC功率MOSFET的雪崩堅固性，以評估轉換器在極端瞬態條件下的可靠性。1700V SiC MOSFET有潛力取代傳統的1700V硅IGBT中壓功率變換器，如800V和1500V鐵路牽引應用。本文采用無箝位電感測試電路，對1700 V SiC MOSFET串聯和并聯的單次雪崩堅固性進行了測試。本文首次報道了串聯SiC MOSFET的單次雪崩堅固性。在這兩種連接中，觀察到失效的MOSFET消耗了連接總雪崩能量的較低份額。

Keywords——medium voltage, silicon carbide, avalanche ruggedness, UIS, single shot, SiC MOSFET

關鍵詞——中壓，碳化硅，雪崩堅固性，UIS，單次，SiC MOSFET

Ⅰ.?Introduction

Silicon carbide (SiC) power devices have received much attention in the last two decades for medium voltage (MV) power applications, such as high speed motor drives, solid state transformers, railway traction and fast chargers for electric vehicles [1]. In medium voltage power converters, typically parallel and series connections of high voltage silicon IGBTs are employed to meet the high voltage and high current requirements. Series connection of power devices are typically used when the high voltage rated devices are not available. Moreover, with a N-fold increase in the voltage rating of SiC power MOSFETs, the on-state resistance of the drift region increases approximately by a factor of N^2.5.Therefore, it is preferred to connect SiC MOSFETs in series in order to reduce total conduction losses of the series string, even though it may result in additional switching losses due to the voltage balance requirements. Series connection of 1.7kV and 10kV SiC MOSFETs have been demonstrated earlier in MV power converters [2], [3], [4]. Parallel connection of power modules are usually required when the current rating of the individual module does not meet the total current requirement. Parallel operation needs special current balancing circuit to mitigate static and dynamic current imbalance among the modules due to inherent mismatch in the output characteristics and the circuit layout. Dedicated current balancing techniques for SiC power MOSFET?modules have been reported earlier in [5], [6].

在過去二十年中，碳化硅（SiC）功率器件在中壓（MV）功率應用中受到了廣泛關注，如高速電機驅動、固態變壓器、鐵路牽引和電動汽車快速充電器[1]。在中壓功率變換器中，通常采用高壓硅IGBT并聯和串聯的方式來滿足高壓大電流的要求。在沒有高額定電壓設備時，通常采用電源設備的串聯連接。此外，隨著SiC功率MOSFET的額定電壓增加n倍，漂移區的導通電阻大約增加了N^2.5倍。因此，為了減少串聯串的總導通損耗，最好將SiC MOSFET串聯起來，盡管由于電壓平衡的要求，可能會導致額外的開關損耗。1.7kV和10kV SiC MOSFET的串聯連接早前已在中壓功率變換器中得到演示[2]，[3],[4]。當單個模塊的額定電流不滿足總電流要求時，通常需要并聯電源模塊。并聯運行需要特殊的電流平衡電路，以緩解由于輸出特性和電路布局的固有不匹配而導致的模塊間靜態和動態電流不平衡。SiC功率MOSFET模塊的專用電流平衡技術已經在[5]，[6]中有所報道。

Short circuit and avalanche characteristics of the power MOSFET?are two important parameters, which are used to establish the reliability of the power converter in extreme transient conditions. A power MOSFET?can be characterized for avalanche ruggedness in single shot operation or repetitive operation. When SiC MOSFETs are operated in series or parallel connections, that combination must be characterized for its avalanche ruggedness. This research focuses on the single shot avalanche characterization of these two combinations of the SiC power MOSFETs.

功率MOSFET的短路和雪崩特性是決定功率變換器在極端瞬態條件下可靠性的兩個重要參數。功率MOSFET在單次或重復操作中具有雪崩堅固性。當SiC MOSFET以串聯或并聯方式工作時，這種組合必須具有雪崩堅固性。本文主要研究了這兩種SiC功率MOSFET組合的單次雪崩特性。

800 V dc bus based systems are traditionally used in railway traction applications. Recently, 800 V system has been proposed for the fast chargers in electric vehicle applications. 1700 V SiC MOSFETs have potential to replace the conventional 1700 V silicon IGBTs in these 800 V dc systems. Few railway applications also have 1500 V dc rail systems, where series connection of 1700 V SiC MOSFETs can be used to meet the voltage requirement. In most of these high power applications, parallel connection of the 1700 V MOSFET?modules are required to meet the high current requirement. Avalanche ruggedness of 1700 V SiC MOSFETs have been reported for single module operation in [4], [7]. Considerations in parallel connection of low voltage silicon MOSFETs have been discussed in [8]. An experimental report with the support of numerical simulations for parallel-connected 1200 V SiC MOSFETs have been discussed in [9]. However, little has been reported on the avalanche characteristics of series connected SiC MOSFETs. There remains a need for investigation of the avalanche ruggedness of parallel-connected 1700 V SiC MOSFETs as well.

基于800V直流母線的系統傳統上用于鐵路牽引應用。最近，人們提出了800 V系統用于電動汽車的快速充電器。1700 V SiC MOSFET有潛力在這些800 V直流系統中取代傳統的1700 V硅IGBT。很少有鐵路應用也有1500 V直流軌道系統，其中可以使用1700 V SiC MOSFET的串聯連接來滿足電壓要求。在大多數高功率應用中，需要并聯1700 V MOSFET模塊以滿足高電流要求。在[4]，[7]中已經報道了1700 V SiC MOSFET在單模塊操作下的雪崩堅固性。在[8]中討論了低壓硅MOSFET并聯的注意事項。本文討論了并行連接1200 V SiC MOSFET的實驗報告和數值模擬支持。然而，關于串聯SiC MOSFET的雪崩特性的報道很少。此外，還需要對并聯1700 V SiC MOSFET的雪崩堅固性進行研究。

In this paper, the single shot avalanche ruggedness of series-connected SiC power MOSFETs is reported for the first time. Parallel-connected 1700 V SiC MOSFETs are characterized to understand their behavior during the single shot avalanche condition. The single shot avalanche characteristics are obtained by the widely used unclamped inductive switching (UIS) test circuit. The 1700 V SiC MOSFETs have been characterized in single, series and parallel combinations in the individual tests. Two MOSFETs are used in the series and in the parallel combinations.

本文首次報道了串聯SiC功率MOSFET的單次雪崩堅固性。對并聯的1700 V SiC MOSFET進行了表征，以了解其在單次雪崩條件下的行為。單次雪崩特性是通過廣泛使用的無箝位電感開關（UIS）測試電路獲得的。在單個測試中，1700 V SiC MOSFET具有單、串聯和并聯組合的特性。兩個MOSFET用于串聯和并聯組合。

Ⅱ.Test Methodology

Methodology to qualify SiC MOSFETs for single shot avalanche events has been discussed in [10]. A UIS test circuit, as shown in Fig. 1, has been used earlier for the single shot avalanche characterization of the 10 kV SiC MOSFETs [11]. In this work, a similar UIS test circuit, was used for the avalanche characterization of the SiC MOSFETs. The dc bus capacitor bank was built using high voltage metal film capacitors. A low current high voltage power supply (HVPS) was used to charge the dc bus to obtain the required VDD, and then the HVPS was disconnected from the capacitor bank through a high voltage relay. Optical fiber cable was used for transmitting the gate signal to the DUT. The inductor L was charged by turning on the device under test (DUT). When the inductor current reached the desired value, the DUT gate signal was turned-off to force the DUT into avalanche condition. The DUT voltage and current waveform were recorded using high bandwidth high voltage differential probe and current probe respectively. Stored energy in the inductor L was incremented gradually to reach the critical value at which the DUT failed permanently. IAV and VAV are the peak of the DUT current at the start of the avalanche event and the DUT voltage during the avalanche event respectively. EAV is the total energy dissipated in the DUT during the avalanche event.

在[10]中討論了使SiC MOSFET適應單次雪崩事件的方法。如圖1所示的UIS測試電路，早前已用于10kV SiC MOSFET的單次雪崩表征[11]。在這項工作中，一個類似的UIS測試電路被用于SiC MOSFET的雪崩特性。直流母線電容器組采用高壓金屬膜電容器。采用小電流高壓電源（HVPS）對直流母線進行充電以獲得所需的V_DD，然后通過高壓繼電器將HVPS與電容器組斷開。采用光纖電纜將門信號傳輸到被測設備。電感器L通過打開被測設備（DUT）充電。當電感電流達到所需值時，被測件柵極信號關斷，迫使被測件進入雪崩狀態。采用高帶寬高壓差動探頭和電流探頭分別記錄被測體電壓和電流波形。電感器L中的存儲能量逐漸增加，直至達到被測件永久失效的臨界值。I_AV和V_AV分別是雪崩事件開始時被測體電流的峰值和雪崩事件發生時被測體電壓的峰值。E_AV是雪崩事件期間在DUT中耗散的總能量。

Fig. 2(a) shows the UIS test circuit for the avalanche characterization of series-connected SiC MOSFETs. Two medium voltage gate drivers were used to drive the two DUTs separately. A passive RC snubber based voltage balancing circuit was connected across each of the two DUTs to minimize the voltage imbalance during the test [2]. The test circuit was operated in the similar manner as shown in Fig.
1(b). High bandwidth 6kV, 100 MHz differential voltage probes were used to measure the DUT drain-to-source voltage in the series connection.

圖2(a)顯示了用于串聯SiC MOSFET雪崩特性的UIS測試電路。兩個中壓柵極驅動器分別驅動兩個DUT。在兩個被試之間分別連接了一個基于無源RC緩沖器的電壓平衡電路，以盡量減少測試期間的電壓不平衡[2]。測試電路的操作方法與圖1(b)所示相似。采用高帶寬6kV，100mhz差分電壓探頭，測量被測件漏源電壓。

Fig. 2(b) shows the UIS test circuit for the parallel
connected SiC MOSFETs. A single gate driver with its own isolated dc-dc converter was used to drive the two parallel MOSFETs with an external gate resistor of 33Ω. An internal gate resistor of 4.7Ω was connected in series to the gate of each of the MOSFETs. The UIS test was performed with an intentional current imbalance in the parallel connection to observe the effect of the current mismatch on the avalanche behavior. Two wire strips having approximate inductance of 100nH were introduced in the drain and in the source path of the DUTs, shown as L_d?and L_s
in Fig. 2(b).

圖2(b)顯示了平行連接SiC MOSFET的UIS測試電路。采用帶有隔離DC-DC變換器的單柵驅動器驅動兩個具有33Ω外部柵極電阻的并聯MOSFET。內部柵極電阻4.7Ω串聯到每個MOSFET的柵極上。UIS測試是在并聯中故意設置電流不平衡的情況下進行的，以觀察電流不匹配對雪崩行為的影響。在DUT的漏極和源極路徑中引入兩條電感近似為100nH的導線帶，如圖2(b)中的L_d和L_s所示。

Ⅲ.?Results And Discussion

In this work, 1700V, 40A SiC power MOSFETs were used for the avalanche characterization in series and parallel connection [12]. First, the 1700V MOSFET?was characterized in single operation using the UIS test circuit to determine its critical single shot avalanche energy. Thereafter, the MOSFETs were tested in the series and parallel connection separately. A gate drive voltage of +20V/-5V were employed for switching of the DUTs. New 1700V MOSFETs were used in all the tests. All the tests were performed at room temperature.

在本工作中，使用1700V、40A SiC功率MOSFET在串并聯連接[12]中進行雪崩表征。首先，使用UIS測試電路對1700V MOSFET進行單次工作表征，以確定其臨界單次雪崩能量。然后，分別在串聯和并聯中測試了MOSFET。采用+20V/-5V的柵極驅動電壓進行被測器件的開關。所有測試均采用新型1700V MOSFET。所有試驗均在室溫下進行。

A.?Single MOSFET

The 1700 V SiC MOSFET?was tested using the circuit shown in Fig. 1(a) in the single shot operation. An air core inductor of 8mH was connected in the circuit to store the avalanche energy before dissipating into the DUT. Fig. 3 shows the experimental waveform of the MOSFET?drain-to-source voltage and the drain current. The MOSFET?dissipated total avalanche energy of 1.83J at the peak current of 21A without a failure. In the subsequent experiment, the MOSFET?failed at total avalanche energy of 2.1J.

1700 V SiC MOSFET使用圖1(a)所示的電路在單次操作中進行測試。電路中連接了一個8mH的空芯電感，在雪崩能量消散到被測設備之前存儲雪崩能量。圖3顯示了MOSFET漏極源極電壓和漏極電流的實驗波形。在峰值電流為21A時，MOSFET消耗了1.83J的總雪崩能量而沒有發生故障。在隨后的實驗中，MOSFET在總雪崩能量為2.1J時失效。

B.?Series Connected MOSFETs

Before subjecting the series-connected 1700 V MOSFETs to avalanche condition, a passive RC snubber network was designed and tested for static and dynamic voltage balancing.
RB was selected based on the leakage current values of the two MOSFETs at room temperature. The dynamic balancing network Rs-Cs were selected based on the threshold voltage difference of the MOSFETs along with the inherent delays associated with the individual gate drive channels.

在將串聯的1700 V MOSFET置于雪崩狀態之前，設計了無源RC緩沖網絡，并對其進行了靜態和動態電壓平衡測試。根據兩個MOSFET在室溫下的泄漏電流值選擇R_B。根據MOSFET的閾值電壓差以及與各個柵極驅動通道相關的固有延遲來選擇動態平衡網絡R_S-C_S。

Fig. 4 shows the photograph of the experimental setup for UIS test of the series-connected MOSFETs. Fig. 5 shows the experimental results at total energy of 3.42 J for the series connected MOSFETs without a failure. Both the MOSFETs survived after dissipating 1.72 J and 1.70 J of the avalanche energy. During the avalanche condition, both the MOSFETs were showing approximately equal avalanche voltage.
Thereafter, peak current of the inductor L was increased so that total 4.03 J of the avalanche energy was dissipated in the DUTs. Fig. 6 shows the experimental results in that operating condition. The DUT-2 failed at the avalanche energy of 1.83 J, while the DUT-1 survived even after dissipating a higher avalanche energy of 2.20 J.

圖4顯示了串聯MOSFET的UIS測試實驗裝置的照片。圖5顯示了在總能量為3.42J時串聯MOSFET未失效的實驗結果。在消耗了1.72J和1.70J的雪崩能量后，兩個MOSFET都存活了下來。在雪崩條件下，兩個MOSFET顯示出近似相等的雪崩電壓。此后，電感器L的峰值電流增加，使得雪崩能量在被測件中總共耗散了4.03J。圖6為該工況下的實驗結果。DUT-2在1.83J的雪崩能量下失效，而DUT-1在消耗更高的2.20J的雪崩能量后仍然存活。

C.?Parallel Connected MOSFETs

There is a natural imbalance in the current distribution when two MOSFETs are connected in parallel due to mismatch in the transfer characteristics and the asymmetric parasitic layout in the power and control circuits. For the single shot avalanche characterization of parallel-connected MOSFETs, two 1700 V, 40 A SiC MOSFETs were used with same internal gate resistors. A common gate drive channel was connected in series with an external gate resistor to drive the two parallel MOSFETs. Fig. 7 shows the experimental waveform at total peak current of 30 A and avalanche energy of 4.05 J without a failure. Fig. 7(a) shows the drain current and drain-to-source voltage waveform of the DUTs without a failure. There was an initial imbalance of 10 A in the DUT currents before start of the avalanche event. Power-energy curve of the DUTs are shown in Fig. 7(b). Current and voltage waveform of the DUTs are zoomed-in at the start of the avalanche event, and shown in Fig. 7(c). DUT-2 was carrying the lower share of the total current before start of the avalanche event. Immediately after the DUTs went into avalanche, the DUT-2 switched to carry the higher current, which later started carrying the lower share of the total avalanche current after 1.3 μs as shown in Fig. 7(c). The dissipated avalanche energy in the DUT-1 was higher compared to that in the DUT-2, owing to the higher share of the total current before and during the avalanche condition for most of the time duration.

當兩個MOSFET并聯時，由于傳輸特性的不匹配以及電源和控制電路中的不對稱寄生布局，會導致電流分布的自然不平衡。對于并聯MOSFET的單次雪崩特性，兩個1700 V、40 A的SiC MOSFET使用相同的內部柵極電阻。一個公共柵極驅動通道與一個外部柵極電阻串聯，以驅動兩個并聯的MOSFET。圖7為總峰值電流為30A，雪崩能量為4.05J時無故障的實驗波形。圖7(a)顯示了無故障DUT的漏極電流和漏源電壓波形。在雪崩事件開始之前，DUT電流存在10 A的初始不平衡。被測件的功率-能量曲線如圖7(b)所示。雪崩事件開始時被試的電流和電壓波形放大，如圖7(c)所示。在雪崩事件發生前，DUT-2攜帶的總電流份額較低。如圖7(c)所示，在DUT進入雪崩狀態后，DUT-2立即切換為攜帶較大電流，隨后在1.3μs后，DUT-2開始攜帶雪崩總電流的較低份額。DUT-1的雪崩耗散能量高于DUT-2，這是由于在雪崩發生前和雪崩發生期間的大部分時間內，總電流所占的份額更高。

Total avalanche energy of the UIS test circuit was increased later using the same pair of the DUTs to observe the failure. Fig. 8 shows the experimental drain current and voltage waveform of the DUTs before and after the avalanche event. The DUT-2 failed after dissipating 1.34 J, while the DUT-1 survived the avalanche condition even after dissipating higher avalanche energy of 2.26 J. Fig. 9(a) shows the experimental current and voltage waveform of the DUTs during the avalanche condition. Avalanche power-energy curve of the DUTs are shown in Fig. 9(b). Zoomed-in version of the drain current and voltage waveform of the DUTs at the start and the end of the avalanche event are shown in Fig. 10.
The DUT-1 was carrying higher share of the total current before start of the avalanche event. When the avalanche starts, the DUT-2 took higher share of the current, and again started taking lower share of the current after 1.1 μs. At the end of the avalanche event, the DUT-2 current jumped up, and eventually failed as shown in Fig. 10(b).

隨后使用同一對DUT觀察失效，增加了UIS測試電路的總雪崩能量。圖8為雪崩事件前后被測件實驗漏極電流和電壓波形。DUT-2在耗散1.34J后失效，而DUT-1在耗散更高的雪崩能量2.26J后幸存下來。圖9(a)為雪崩條件下DUT的實驗電流和電壓波形。被試雪崩功率-能量曲線如圖9(b)所示。雪崩事件開始和結束時被試漏極電流和電壓波形的放大版本如圖10所示。在雪崩事件發生前，DUT-1攜帶的總電流份額較高。雪崩開始時，DUT-2的電流占比較高，1.1μs后，DUT-2的電流占比又開始下降。雪崩事件結束時，DUT-2電流跳升，最終失效，如圖10(b)所示。

Ⅳ. Conclusion

Prior works have documented the avalanche ruggedness of single SiC MOSFETs and their failure mechanism. This is the first study to our knowledge to investigate the single shot avalanche ruggedness of series-connected SiC power MOSFETs. In this study we tested the single shot avalanche ruggedness of series and parallel-connected 1700 V SiC power MOSFETs using conventional UIS test circuit. First, the critical avalanche energy of the single SiC MOSFET?was determined by the UIS test circuit to be 2.1 J. During the avalanche failure tests of both the series-connected and the parallel-connected MOSFETs, only one of the MOSFETs failed which had dissipated lower amount of the avalanche energy. The series-combination failed at the total avalanche energy of 4.03 J, while it took 3.60 J of total avalanche energy for the parallel combination of the MOSFETs to fail. In the parallel connected MOSFETs, the slower MOSFET?failed which was carrying the lower share of the current. Future work should include the device physics based analysis to explain the failure of the MOSFET?with lower share of the current in the parallel combination. Also, there remains a need to explain the failure of the MOSFETs with lower dissipated avalanche energy in both the series connection and the parallel connection.

先前的工作已經記錄了單SiC MOSFET的雪崩堅固性及其失效機制。據我們所知，這是第一次研究串聯SiC功率MOSFET的單次雪崩堅固性。在本研究中，我們使用傳統的UIS測試電路測試了1700V SiC功率MOSFET串聯和并聯的單次雪崩堅固性。首先，UIS測試電路確定單SiC MOSFET的臨界雪崩能量為2.1J。在串聯和并聯MOSFET的雪崩失效測試中，只有一個MOSFET損耗了較低的雪崩能量。串聯組合在總雪崩能量為4.03J時失敗，而并聯組合在總雪崩能量為3.60 J時失敗。在并聯的MOSFET中，承載較低電流份額的較慢的MOSFET失效。未來的工作應該包括基于器件物理的分析，以解釋在并聯組合中具有較低電流份額的MOSFET的故障。此外，仍然需要解釋在串聯連接和并聯連接中具有較低損耗雪崩能量的MOSFET的失效。

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