2.5D先進封裝介紹（視頻）

2.5D先進封裝介紹（視頻）

Hello everyone, welcome to Samsung. Today I'd like to talk about 2.5 d package technology, which is one of the hottest topics in package technology. First of all, what is 2.5 deep package technology?

大家好，歡迎來到我的節(jié)目。今天我們談?wù)?.5D封裝技術(shù)，這是封裝技術(shù)中最熱門的話題之一。首先，什么是2.5D封裝技術(shù)？

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2.5 d looks like this. It is the packaging technology using silicone interpreter to connect dies on it. And silicon interposa has tsb through silicon via fabrical electrical interconnection. Then this silicon interpreter with dice are placed on package substrate to make package. Those dies can be multiple logic dies or logic die plus memory die. Prologic dies it can be f p g. Dies, g p u. Dies or network dies. This is the simplified structural 2.5 d to explain function of.

2.5D封裝看起來像這樣。它是使用具有硅通孔技術(shù)的interposer將不同的芯粒進行連接的技術(shù)。Interposer 嵌入在基板中，或者下面與基板相連，上面露出連接點，這樣就可以將多個芯粒放置在連接點上 。這些芯粒的類型可以是邏輯芯片，高寬帶存儲的HBM，GPU等。 這是個簡化版的示意圖，可以看到最下層是基板，然后中間層是具有硅通孔技術(shù)的interposer，最上層是邏輯芯粒和存儲芯粒。

Type of silicone interpreter to connect logic die and memory die. For this case tap side of silicone temperature is also called as front side. More in detail, silicone interpreter has 3 part vertically. At top there is b e o l, back end of line layer which uses copper for electrical interconnection. If lining space of this carpet trace is fine less than 1μm it uses pol layer pie process but it can also use ideal for course copper trace at the middle there is tsp through silicon beer robotical electrical interconnection as its name implies tsp is a beer go through silicone supporter robotical electrical interconnection at the bottom there is r d l because it usually calls cafa trace bottom side of silicone interposter is also called as backside.

再看看更詳細的示意圖，Interposer 大致分為三層，最上面的一層是BEOL層，中間是TSV 硅通孔層，最下面是BSRDL層。BEOL層也叫back end of line layer, 利用銅層進行連接。TSV 硅通孔層用于連接上下兩層。BSRDL 層也叫back side 重布線層。Interposer起到類似橋梁的作用將基板與芯粒連接起來。

Let's compare 2 d and 3 d to understand what is 2.5 d to the package. Is conventional package structure with dye with wire wounding or primitive. It also can be more than 2 dice side by side or stack dice, but they are not connected each other directly. How about 3 d? As you can see in the picture, chip a is connected with chip b with micro bump and chip b is connected with packet substrate at the bottom. Through tsb. We call this structure as ready.

讓我們對比一下2 D和3D封裝的區(qū)別，這樣可以更好的了解什么是2.5D。2D 是傳統(tǒng)的封裝形式，芯粒通過wire bounding 的線連接與基板相連，或者通過基板上的C4與芯粒上的BUMP進行連接。2D也可以同時放置多個芯粒，但這些芯片互相不會堆疊在一起，互相通信通過基板相連。而3D是什么樣的呢？如圖所示，芯粒A與芯粒B通過微凸點連接，芯粒B 通過TSV與底部的基板連接。

What is the difference between 2.5 d and 3 d? Dies in 2.5 z package are electrically connected through silicone interposa, but Dyson 3 d is electrically connected directly. 2.5 d has tsb in silicone interposa, but 3 d has tsb in dice or one of dice cheaply for this case. This is an example of 2.5 d for fpgas.

2.5D和3D進一步還有什么具體的區(qū)別呢？如示意圖所示，2.5D封裝的芯片通過interposer將兩個芯粒進行連接。而3D封裝則是兩個芯粒堆疊并直接相連，其中一個芯粒直接與基板連接。 3D封裝中的一個芯粒具有TSV 硅通孔結(jié)構(gòu)。

Jailing's apj company breaks one big apga die into 4 pieces, then put on silicone interpreter to connect each other. Because if you make vapors with big fpz dyes, die yield will be low, but if he split into smaller dyes die yield will be better.

這是一個2.5D FPBGA的芯片，整個芯片由4個芯粒組合而成，中間為interposer層將芯粒與基板連接。為什么要不直接組成一個芯粒呢？這主要是成本的考慮。小的芯粒良率更高，成本更低。

In 2012, jailings announced industry first 2.5, the package with silicone interpreter for their apga product. Another example is per GPU from AMD. In 2015 AMD combined GPU and hpm. Compare with previous solution GPU plus gddr gripping memory. Its size was much smaller with better performance. This is cross section of GPU plus hpm combination. Hpm by itself also have multiple DM dye stacks and tsp inside of DM dye. Sem's image of actual product looks like this. Nbdia also had GPU plus HBM combination in 2016.

2012年，賽靈思發(fā)布了業(yè)界第一款2.5D 封裝的FPGA 產(chǎn)品。另外一個產(chǎn)品是AMD 2015年發(fā)布的GPU。AMD這款GPU結(jié)合了GPU和高寬帶存儲的HBM 。與以前的解決方案相比，這款GPU尺寸更小，性能更好。這是GPU加HBM的橫截面示意圖。HBM本身也有多個芯粒堆疊。實際產(chǎn)品的SEM圖看起來像這樣。英偉達在2016那年也有類似的GPU加HBM的組合產(chǎn)品。

Stiepener at peripuri is to minimize package warpiece. Another example is broadcom network switch in 2018. It integrated network switch die and hpm memory on silicon interposa. Typically silicone interpreter is made by a foundry and major players are tsmc, umc, global founders, etc. In 2020 tsmc announced their latest 2.5. This solution with huge silicone temperature. It has 2 processor dies at the center and 8 hpm modules around. It uses 2000500mm2 size silicone interpreter and tsmc plan to start mass production from 2023 this is a brief introduction to 2.5 deep package technology with silicone interposa I hope this can help you to understand basic two point five the package technology have a nice day and see you again soon bye bye.

Stiffener 是外面的加強框架，主要是來減少基板翹曲變形。另一個例子是2018年Broadcom的產(chǎn)品。它將網(wǎng)絡(luò)交換機芯粒和HBM存儲器芯粒通過interposer集成在基板上。通常2.5D封裝由代工廠制造，當前的主要參與者有臺積電、聯(lián)電、格芯等。2020年臺積電宣布了他們最新的2.5D封裝。這種產(chǎn)品具有2個處理器芯粒，周圍有8個HBM芯粒。它使用的interposer 有2500mm2。希望這個視頻可以幫助你了解2.5D封裝技術(shù)，再見。

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